1. Field of the Invention
The present invention relates to a variable gain amplifier circuit for amplifying an input signal with a geometrically controlled gain in accordance with a digital control signal.
2. Related Background Art
Up to now, as shown in FIG. 8, a conventional variable gain amplifier for amplifying an input signal with a geometrically controlled gain in accordance with an n-bit digital control signal includes: an operational amplifier; (2n+1) capacitors in each of which one terminal is connected to an reverse input terminal of the operational amplifier; and switches for connecting the other terminals of (2n−1) of the capacitors to an input terminal or an output terminal. The switches are controlled in accordance with an output of an n-bit decoder.
Here, more specifically, it is assumed that a variable gain amplifier geometrically controls input and output gains between 0.5 times to 4 times using an 8-bit digital signal. If the total capacitance is 10 pF, capacitance fixedly connected between the input terminal and the reverse input terminal of the operational amplifier will be 3.3333 pF, capacitance fixedly connected between the output terminal and the reverse input terminal of the operational amplifier will be 2 pF, capacitance whose connection is first switched from the output terminal to the input terminal will be 0.0181 pF, and capacitor whose connection is finally switched from the output terminal to the input terminal will be 0.0131 pF. Therefore, a ratio between the fixedly connected capacitance and the capacitance whose connection is switched becomes 100 times or more, so that it is hard to realize these capacitances with high precision. In addition, the number of capacitors switched between the input terminal and the output terminal and the number of switches becomes 255. Therefore, even when the variable gain amplifier is realized, an increase in layout area is caused.
A second conventional art with respect to a variable gain amplifier, as shown in FIG. 9, is a circuit in which an m-bit variable gain amplifier and an (n-m)-bit variable gain amplifier are connected in series with each other. More specifically, it is assumed that the variable gain amplifier that geometrically controls the input and output gains between 0.5 times to 4 times using the 8-bit digital signal and a 4-bit variable gain amplifier are connected as two stages in series with each other. In case that variable gain range of the variable gain amplifier of the preceding stage is set to 0.5 times to 3.5395 times to be controlled using upper 4-bits, capacitance fixedly connected between the input terminal and the reverse input terminal of the operational amplifier will be 3.3333 pF, capacitance fixedly connected between the output terminal and the reverse input terminal of the operational amplifier will be 2.2029 pF, capacitance whose connection is first switched from the output terminal to the input terminal will be 0.2960 pF, and capacitance whose connection is finally switched from the output terminal to the input terminal will be 0.2323 pF. In case that a variable gain range of the variable gain amplifier of the following stage is set to 1 time to 1.1301 times to be controlled using lower 4-bits, capacitance fixedly connected between the input terminal and the reverse input terminal of the operational amplifier will be 5 pF capacitance fixedly connected between the output terminal and the reverse input terminal of the operational amplifier will be 4.6946 pF capacitance whose connection is first switched from the output terminal to the input terminal will be 0.0204 pF and capacitance whose connection is finally switched from the output terminal to the input terminal will be 0.0203 pF.
Because a capacitance ratio in the following stage is equal to or larger than 100 times, a structure as shown in FIG. 10 may be used in order to reduce the capacitance ratio. According to the structure, a capacitor is inserted between the reverse input terminal of the operational amplifier and the capacitors whose connections are switched between the input and output terminals. Therefore, an effective capacitance value can be reduced to reduce the capacitance ratio. Assume that the inserted capacitor and the switched capacitors each have the same capacitance for ease of calculation. Then, capacitance fixedly connected between the input terminal and the reverse input terminal of the operational amplifier will be 5 pF, capacitance fixedly connected between the output terminal and the reverse input terminal of the operational amplifier will be 4.6549 pF and inserted capacitance and capacitances whose connections are switched from the output terminal to the input terminal will be 0.3676 pF. When the switched capacitors have the same capacitance, a gain error is up to 0.0034% to be sufficiently small, thereby being negligible. In the case of such a structure, two operational amplifiers are required. However, the number of capacitors and the number of switches, which compose a feedback loop can be greatly reduced to about 30. In addition, it is easy to realize because a structure of the decoder is simplified. However, a noise is caused in each amplifying stage. Therefore, a noise characteristic deteriorates as compared with the first conventional art.